1. Field of the Invention
The present invention generally relates to clocking systems for electronic circuits, and more particularly to a method of determining which of a plurality of different operating modes is to be used by a circuit, which is adapted to receive a variety of external clock signals.
2. Description of the Related Art
Various types of electronic circuits have been constructed that support a wide range of different clock modes. For example, data converters can operate in different speed modes in which different master clock rates and sample clock rates are used. A digital-to-analog converter might have two operating modes, such as a base mode and a high mode, depending on what master clock rate and sample clock rate are being provided from the front-end circuitry. This capability allows a single converter to support multiple applications and gives the end-user (i.e., the final product manufacturer) greater flexibility in the design of the overall electronic system.
A conventional digital-to-analog converter (DAC) 10 is illustrated in FIG. 1 and includes a digital (binary) signal source 12, which provides the primary input to a delta-sigma modulator 14. The digital signal source could be from, e.g., a digital radio receiver, an audio compact disc (CD), a digital audio tape (DAT), a digital video disc (DVD), a broadcast satellite, or personal computer (PC) audio. Delta-sigma modulator 14 feeds a multilevel noise-shaped signal based on the digital input stream to a multi-level pulse-density modulation (PDM) encoder 16. PDM encoder 16 turns the signal from delta-sigma modulator 14 into a multi-level, discrete-time analog signal. Low-pass filter 18 removes high frequencies from the output, and the filtered output then drives some other device such as a speaker 20.
Conventional data converters have dramatically grown in complexity and capability, and their clocking systems have also grown in complexity to more fully utilize the function and high performance provided by CMOS technology. A typical clocking system can provide a multiplicity of timing signals to the internal converter elements and to external devices. These clocks define the timing cycle for the data flow of the machine. Some clock signals can be non-overlapping and serve to isolate one cycle of operation from the next cycle, while other clock signals overlap so as to gain a performance advantage by anticipating the next cycle of operation. The positioning in time of these clocks is very critical for high performance, particularly for circuits such as DACs which operate in a pipelined manner, that is, are divided into separate stages such that a single DAC can actually be simultaneously performing multiple tasks for different (successive) data sequences during a single clock cycle. However, this scheme requires precise timing. External device considerations may also require fairly exact timing signals. Clock design becomes further complicated when a DAC must support a variety of external clock inputs.
DAC 10, for example, might support frequency ranges from a sample rate of 2 kHz and master clock rate of 0.5 MHz, to a sample rate of 192 kHz and a master clock rate of 48 MHz, all as part of distinct internal operating modes. The master clock signal is used to derive most of the control signals for the components of DAC 10, and the sample rate signal represents the sampling rate for the encoder which previously created the digital signal stream from an original analog source. CDs typically use a sampling rate of 44.1 kHz, PC audio uses a sampling rate of 48 kHz, DVDs use a sampling rate of 96 kHz, and other high-end equipment can use a sampling rate of up to 192 kHz. Depending upon the particular operating mode that is selected, any or all of the components within DAC 10 (modulator 14, PDM encoder 16, and/or filter 18) might operate in a different manner.
Some devices provide a control port or other input that allows the user to explicitly select the desired clock configuration. However, this approach requires a higher pin count on the external physical interface for the integrated circuit (IC) which constitutes the device and assumes that the front-end circuitry will provide the mode selection signal. Accordingly, some converters have been devised which automatically determine the appropriate clock configuration based on the sample rate clock (or left/right clock, “LRCK”) and master clock (“MCLK”) frequencies. For instance, if the end-user provides an LRCK of 48 kHz and an MCLK of 12 MHz, these rates might imply a base mode of operation for the DAC, while a 96 kHz LRCK rate and a 12 MHz MCLK rate might imply a high mode of operation. The appropriate mode can be determined for these cases by simply examining the ratio of MCLK to LRCK, i.e., by counting the number of high signals for MCLK in an LRCK period. If the ratio is around 256, the base mode is enabled, and if the ratio is around 128, the high mode is enabled.
As digital signal processing technology improves and changes, a wider variety of clock rates must be supported to allow a single converter to be used in a growing number of applications. Unfortunately, existing solutions for establishing the proper clock configuration have become inadequate as more clock rate combinations are employed. For example, devices which utilize an LRCK of 48 kHz and an MCLK of 12 MHz currently exist for operation at a base rate, and other devices which utilize an LRCK of 96 kHz and an MCLK 24 MHz for operation at a high rate. Supporting both of these clock configurations would be preferable. However, the MCLK/LRCK ratio is the same for both (around 256) and selection of the base mode would result in improper operation for the latter case.
Another solution for determining the clock configuration examines the MCLK rate by comparing it to an internally generated frequency. A single comparison frequency can be so used for a wide range of MCLK rates, by dividing the MCLK signal using increasing integer values until it is at or near the internally generated value. A device that supported MCLK rates of 12 MHz, 18 MHz and 24 MHz could use a comparison frequency of 6 MHz and divide the MCLK signal successively by the integers 2, 3, and 4 until the quotient was around 6 MHz. This approach, however, also becomes unfeasible as alternative clock configurations arise which utilize the same master clock frequency and with more variation in the master clock rates.
In light of the foregoing, it would be desirable to devise an improved method for determining which of a plurality of clock configurations is to be used for an electronic device, such as a data converter. It would be further advantageous if the method were not solely dependent on either a master clock rate value or a ratio of two external clock signals.